1. Field of the Invention
The present invention generally relates to semiconductor devices, and more particularly, to a very-high-speed semiconductor device having a short gate length and manufacturing method thereof.
2. Description of the Related Art
With the progress of miniaturization technology, the gate length of 0.1 μm or less is becoming possible in today's very-high-speed semiconductor devices, and attempts have been made to realize a very high speed operation using such ultra-miniaturized semiconductor devices.
On the other hand, in such ultra-miniaturized semiconductor devices, as a result of reducing the gate length, a so-called short channel effect tends to occur and punch-through of carriers is apt to occur between the source region and the drain region.
Consequently, as shown in FIG. 1, in the conventional ultra-miniaturized semiconductor devices, pocket implantation is performed so as to control the short channel effect, and channel stop implantation is performed so as to control punch-through.
FIG. 1 shows the construction of a conventional p-channel MOS transistor 10 having a pocket implantation region and a channel stop implantation region.
Referring to FIG. 1, a device region 12A is defined by element isolation regions 12B of the STI structure on a p-type Si substrate 11 on which an n-type well 12 is formed. An n-type channel stop region 12C is formed in the device region 12A by ion implantation of an n-type impurity element.
On the other hand, in the device region 12A, a gate electrode 14 corresponding to a predetermined channel region is formed on the Si substrate 11 via a gate insulating film 13. In the device region 12A, a p+ type source region 12S and a drain 12D are formed on both sides of the gate electrode 14, respectively, each being distant from a sidewall surface of the gate electrode 14 at a distance equal to the thickness of a sidewall insulating film formed on the sidewall surface. In addition, a p-type source extension region 12Se and a drain extension region 12De extend under the sidewall insulating film from the source region 12S and the drain region 12D, respectively. A channel is formed between the end of the source extension region 12Se and the end of the drain extension region 12De.
Further, in the device region 12A, n-type pocket regions 12P are formed so as to contain the source extension region 12Se and the drain extension region 12De and to extend further downward than a part where an inversion layer constituting the channel is formed.
In the p-channel MOS transistor thus constructed, since the n-type channel stop region 12C is formed under the channel region, the entry of carriers into a deep part of the device region 12A is controlled. Thus, punch-through between the source region 12S and the drain region 12D is controlled. Additionally, since the source extension region 12Se and the drain extension region 12De are contained in the n-type pocket regions 12P, extension of a depletion layer from the drain region is controlled when a MOS transistor is in operation. Thus, short channel effect is controlled. As a result, roll-off characteristics of the MOS transistor are improved. Such pocket regions 12P can be formed by oblique ion implantation using the gate electrode 14 as a mask.
Similar constructions can be formed with respect to n-channel MOS transistors.
On the other hand, in the MOS transistor on which such pocket implantation is performed, when the gate length is further reduced, it is necessary to further increase the impurity concentration of the pocket regions 12P.
When the impurity concentration of the pocket region 12P is increased, however, the impurity element forming the pocket regions 12P gains entrance into the region directly below the gate electrode 14. As a result, the impurity concentration increases in the channel surface. Hence, a problem of degradation of mutual conductance arises, accompanying the decrease of mobility due to the scatter of the carriers.
In addition, when such pocket regions 12P are formed, substrate impurity concentration in the vicinity of the source or drain region is increased. Consequently, the width of the depletion layer that is formed around the source region 12S or the drain region 12D is decreased. Hence, problems such as increase in junction capacitance and increase in junction leakage current occur.
On the other hand, conventionally, Japanese Laid-Open Patent Application No. 6-37309 proposes to perform oblique ion implantation from surroundings of a gate electrode so as to form a punch-through stopper region in the central region of a channel.
FIG. 2 shows the construction of a semiconductor device 20 according to the above-described proposal.
Referring to FIG. 2, the semiconductor device 20 is an n-channel MOS transistor. A device region 21A defined by device isolation films 21B is formed on a p-type Si substrate 21. A gate electrode 23 is formed on the device region 21A via a gate insulating film 22.
In addition, in the device region 21A, n-type LDD regions 24Sd and 24Dd, corresponding to both ends of the gate-electrode 23, are formed. Further, an n+ type source region 24S and an n+ type drain region 24D, corresponding to the outer ends of sidewall insulating films 23S of the gate electrode 23, are formed.
Additionally, in the conventional semiconductor device 20 in FIG. 2, in the device region 21A, a p-type region 25 is formed as a punch-through stopper region between the LDD regions 24Sd and 24Dd.
FIG. 3 shows the forming process of such a longitudinal punch-through stopper region 25.
Referring to FIG. 3, the Si substrate 21 is rotated about the axis that passes through the gate electrode 23, and by performing ion implantation of B+ at an angle, the punch-through stopper region 25 is formed as an overlapping part of the ion implantation.
As described above, in the construction shown in FIG. 2, the B concentration of the punch-through stopper region 25 is increased only to approximately twice as much as that of the surrounding region at best. Thus, there is no guarantee that the punch-through stopper region 25 will function as an effective punch-through stopper region. Also, in FIGS. 2 and 3, the punch-through stopper region 25 is illustrated to extend in the direction perpendicular to the principal surface of the substrate 21. The shape of the punch-through stopper region 25 is, however, determined by the distribution of B in the ion implantation process of FIG. 3. Accordingly, there is a possibility that the punch-through stopper region 25 will not always be formed into a narrow shape extending in the direction perpendicular to the substrate surface.
FIG. 4 shows the relationship between substrate impurity concentration and OFF current in a case where the punch-through stopper region 25 is eliminated from the MOS transistor in FIG. 2. FIG. 5 is a device simulation result showing the relationship between the substrate impurity concentration and junction capacitance in the same MOS transistor.
As can be seen from FIG. 4, the OFF current is decreased as the substrate impurity concentration is increased. This shows the reduction of the punch-through effect obtained by providing an inversion channel and a reverse conducting type region in the channel region. For example, it is recognized that the OFF current can be reduced to equal to or less than approximately 1×10−9 A/μm by increasing the substrate impurity concentration to equal to or more than 3×1018 cm−3.
On the other hand, referring to the relationship shown in FIG. 5, the junction capacitance in the source region 24S or the drain region 24D is increased as the substrate impurity concentration is increased. For example, it is recognized that the substrate impurity concentration needs to be set equal to or less than 1×1018 cm−3 if an attempt is made to decrease the junction capacitance to equal to or less than 3×10−15 F/μm.
As described above, it is impossible to make the control of punch-through and the reduction of the junction capacitance compatible in the structure without a punch-through stopper region. On the other hand, as shown in FIG. 1, with the construction where the high-concentration channel stop region 12C is provided between the source region 12S and the drain region 12D, it is impossible to prevent the junction capacitance from being increased. In addition, in the construction shown in FIG. 2, it is conceived that the effect of the punch-through stopper region is insufficient.